Decoding double-error-correcting Reed-Solomon codes

The decoding of double-error-correcting (DEC) Reed-Solomon (RS) codes is considered. It is shown that by modifying a well known decoding algorithm for DEC RS codes and solving the error-locator polynomial by Berlekamp´s method for solving quadratic equations, efficient hardware architectures can be derived. Furthermore, these architectures are particularly suited to implementation over the dual basis. As an example, the architecture of a (15, 11) RS codec is described. The approaches discussed here also lend themselves to the decoding of double-error-correcting/triple-error-detecting RS codes and allow for reduced decoding times compared with alternative approaches to decoding these codes