Title :
Profit Aware Circuit Design Under Process Variations Considering Speed Binning
Author :
Datta, Animesh ; Bhunia, Swarup ; Choi, Jung Hwan ; Mukhopadhyay, Saibal ; Roy, Kaushik
Author_Institution :
Qualcomm Inc., San Diego, CA
fDate :
7/1/2008 12:00:00 AM
Abstract :
In this paper, a profit-aware design metric is proposed to consider the overall merit of a design in terms of power and performance. A statistical design methodology is then developed to improve the economic merit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve economic gain of a design over its initial yield-optimized design. Finally, we present an integrated design methodology for simultaneous sizing and bin boundary determination to enhance profit under an area constraint. Experiments on a set of ISCAS´85 benchmarks show in average 19% improvement in profit for simultaneous sizing and bin boundary determination, considering both leakage power dissipation and delay bounds compared to a design initially optimized for 90% yield at iso-area in 70-nm bulk CMOS technology.
Keywords :
CMOS integrated circuits; circuit optimisation; integrated circuit design; integrated circuit yield; statistical analysis; bin boundary determination; bulk CMOS technology; delay bounds; economic gain; economic merit; frequency binning; integrated design methodology; leakage power dissipation; low-complexity sensitivity-based gate sizing algorithm; process variations; product price profile; profit aware circuit design; profit-aware design metric; simultaneous sizing; size 70 nm; speed binning; statistical design methodology; yield-optimized design; Algorithm design and analysis; CMOS technology; Circuit synthesis; Delay; Design methodology; Design optimization; Frequency; Integrated circuit technology; Integrated circuit yield; Power generation economics; Design for profit; frequency-binning; gate-level sizing; leakage power; statistical delay variation;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2008.2000364
