Case Study of Reliability-Aware and Low-Power Design

Author

Yang, Shengqi ; Wang, Wenping ; Lu, Tiehan ; Wolf, Wayne ; Vijaykrishnan, N. ; Xie, Yuan

Author_Institution

Digital Home Group, Intel Corp., Chandler, AZ

Volume

16

Issue

7

fYear

2008

fDate

7/1/2008 12:00:00 AM

Firstpage

861

Lastpage

873

Abstract

Based on the proposed reliability characterization model, reliability-aware and low-power design is illustrated for the first time as a design methodology to balance reliability enhancement and power reduction. Low-power and reliable SRAM cell design, reliable dynamic voltage scaling (DVS) algorithm design, and voltage island partitioning and floorplanning for reliable system-on-a-chip (SOC) design are demonstrated as case studies of this new design methodology.

Keywords

SRAM chips; integrated circuit layout; integrated circuit reliability; logic partitioning; low-power electronics; system-on-chip; SRAM cell design; circuit reliability; dynamic voltage scaling algorithm design; low-power design; power reduction; reliability characterization model; reliability enhancement; reliability-aware design; system-on-a-chip design; voltage island partitioning; Algorithm design and analysis; Circuits; Design methodology; Dynamic voltage scaling; Energy consumption; Power system reliability; Random access memory; Reliability engineering; System-on-a-chip; Voltage control; Circuit reliability; SRAM; dynamic voltage scaling (DVS); low power; systems-on-a-chip (SOC); voltage island partitioning and floorplanning;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2008.2000460

Filename

4553751