Title :
Glitch reduction in second-generation SI circuits
Author :
Oliaei, O. ; Loumeau, P.
Author_Institution :
Electron. Dept., Ecole Nat. Superieure des Telecommun., Paris, France
fDate :
4/13/1995 12:00:00 AM
Abstract :
A simple method for reducing the glitches of second-generation SI circuits is presented. For a given SI circuit it is sufficient to apply this technique only to the last stage
Keywords :
active networks; switched current circuits; active networks; circuit stages; glitch reduction; second-generation SI circuits; switched current circuits;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19950437
