Title :
Array multiplication scheme using (p, 2) counters and pre-addition
Author :
Vassiliadis, S. ; Hoekstra, J. ; Chiu, H.-T.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
fDate :
4/13/1995 12:00:00 AM
Abstract :
The authors propose a pre-add counter scheme that provides for common operand lengths and a speedup, measured in terms of CSAs, by a factor of up to 9 over CSA array multipliers and by a factor up to 2 over parallel multipliers using Lim counters. Furthermore, it permits efficient mapping in VLSI implementations
Keywords :
VLSI; digital arithmetic; integrated logic circuits; multiplying circuits; parallel architectures; VLSI implementations; array multiplication scheme; pre-add counter scheme; pre-addition;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19950417
