Title :
Evaluation of sequential-in-random-out memory device
Author :
Chang, C.-Y. ; Hou, T.-W. ; Shieh, C.-K.
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fDate :
4/13/1995 12:00:00 AM
Abstract :
The buffering of data is a potential bottleneck to performance. In general, the buffer can be implemented either by FIFO or dual-port RAM, which are both two-port memory devices. The authors propose a classification of buffers. According to the classification, a new two-port memory device with the sequential-in-random-out feature is introduced. Simulation results show that 45% time, at most, could be saved, as compared to a FIFO buffer
Keywords :
buffer storage; memory architecture; buffer; sequential-in-random-out memory device; two-port memory device;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19950454
