• DocumentCode
    776543
  • Title

    ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-μm CMOS technology

  • Author

    Salman, Akram A. ; Gauthier, Robert ; Putnam, Chris ; Riess, Philipp ; Muhammad, Mujahid ; Woo, Min ; Ioannou, Dimitris E.

  • Author_Institution
    Electr. & Comput. Eng. Dept., George Mason Univ., Fairfax, VA, USA
  • Volume
    3
  • Issue
    3
  • fYear
    2003
  • Firstpage
    79
  • Lastpage
    84
  • Abstract
    Historically, the failure mode of the nMOS/lateral n-p-n (Lnpn) bipolar junction transistor (BJT) due to electrostatic discharge (ESD) is source-to-drain filamentation, as the temperature exceeds the melting temperature of silicon. However, as the gate-oxide thickness shrinks, the ESD failure changes over to oxide breakdown. In this paper, transmission line pulse (TLP) testing is combined with measurements of various leakage currents and numerical simulations of the electric field to examine the failure mode of an advanced 0.1-μm CMOS technology, which is shown to be through gate-oxide breakdown. It is also shown by ID-VG and IG-VG measurements that the application of nondestructive ESD pulses causes gradual degradation of the oxide well before failure is reached, under the (leakage current) failure criteria used. Finally, the latent effects of stress-induced oxide degradation on the failure current If of the nMOS/Lnpn are studied, and it is shown that as the device ages from an oxide perspective, its ESD protection capabilities decrease.
  • Keywords
    CMOS integrated circuits; MOSFET; dielectric thin films; electrostatic discharge; failure analysis; integrated circuit reliability; leakage currents; protection; semiconductor device breakdown; 0.1 micron; ESD failure; ESD-induced oxide breakdown; advanced CMOS technology; electric field; electrostatic discharge; failure mode; gate-oxide breakdown; gate-oxide thickness; gradual oxide degradation; leakage current failure criteria; nMOS/lateral n-p-n BJT; nondestructive ESD pulses; numerical simulations; self-protecting GG-nMOSFET; stress-induced oxide degradation; transmission line pulse testing; CMOS technology; Current measurement; Degradation; Electric breakdown; Electrostatic discharge; Leakage current; MOS devices; Pulse measurements; Temperature; Transistors;
  • fLanguage
    English
  • Journal_Title
    Device and Materials Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1530-4388
  • Type

    jour

  • DOI
    10.1109/TDMR.2003.815275
  • Filename
    1229718