• DocumentCode
    776817
  • Title

    Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method

  • Author

    Yu, Wenjian ; Zhang, Mengsheng ; Wang, Zeyi

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
  • Volume
    25
  • Issue
    1
  • fYear
    2006
  • Firstpage
    12
  • Lastpage
    18
  • Abstract
    Inserting dummy (area fill) metals is necessary to reduce the pattern-dependent variation of dielectric thickness in the chemical-mechanical polishing (CMP) process. Such floating dummy metals affect interconnect capacitance and, therefore, signal delay and crosstalk significantly. To take the floating dummies into account, an efficient method for three-dimensional (3-D) capacitance extraction based on boundary element method is proposed. By introducing a floating condition into the direct boundary integral equation (BIE) and adopting an efficient preconditioning technique, and the quasi-multiple medium (QMM) acceleration, the method achieves very high computational speed. For some typical structures of area fill, the presented algorithm has shown over 1000× speedup over the industry-standard Raphael while preserving high accuracy. Compared with the recently proposed PASCAL in the work of Park et al. (2000), the proposed method also has about ten times speedup. Since the dummies are not regarded as normal electrodes in capacitance extraction, the proposed method is much more efficient than the conventional method, especially in cases with a large number of floating dummies.
  • Keywords
    boundary integral equations; boundary-elements methods; chemical mechanical polishing; design for manufacture; filler metals; integrated circuit interconnections; 3D capacitance extraction; PASCAL; area fill metals; boundary element method; boundary integral equation; chemical-mechanical polishing; design for manufacturability; dielectric thickness; floating dummy metals; floating metal fills; interconnect capacitance extraction; preconditioning technique; quasimultiple medium acceleration; signal delay; Boundary element methods; Capacitance; Crosstalk; Delay; Dielectrics; Electrodes; Integral equations; Integrated circuit interconnections; Manufacturing; Very large scale integration; Boundary-element method (BEM); design for manufacturability; dummy fill; interconnect capacitance extraction;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2005.853690
  • Filename
    1564300