Title :
Algorithm to extract two-node bridges
Author :
Zachariah, Sujit Thomas ; Chakravarty, Sreejit
Author_Institution :
Design Technol., Intel Corp., Santa Clara, CA, USA
Abstract :
Current bridge fault extraction techniques are limited by performance and capacity constraints. In this paper, we present a fast and accurate algorithm to extract and rank two-node bridges based on the computation of their weighted critical area. Experimental results showing the algorithm´s performance are presented.
Keywords :
VLSI; circuit analysis computing; fault diagnosis; integrated circuit layout; integrated circuit testing; probability; bridge fault extraction technique; defect-based testing; high-probability defects; layout analysis; rectangle intersections; two-node bridge extraction algorithm; weighted critical area; Bridge circuits; Circuit faults; Circuit testing; Content addressable storage; Data analysis; Data mining; Geometry; Manufacturing; Merging; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2003.816141
