A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider

Author

Lu, Ivan Siu-Chuang ; Weste, Neil ; Parameswaran, Sri

Author_Institution

Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW

Volume

54

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

323

Lastpage

327

Abstract

This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The divider operates as a voltage controlled ring oscillator with the output frequency modulated by the switching of the input transmission gate. The divider, designed in a 0.25-mum SOS-CMOS technology, occupies 35times25 mum² and exhibit a operating frequency of 5.6 GHz while consuming 79 muW at a supply voltage of 0.8 V. Process and temperature tolerant operation can be achieved by utilizing a novel compensation circuitry to calibrate the speed of the ring oscillator-based divider. The simple compensation circuitry contains low-speed digital logic and dissipates minimal additional power since it is powered on only during the one-time factory calibration sequence

Keywords

CMOS logic circuits; MMIC frequency convertors; frequency dividers; voltage-controlled oscillators; 0.25 micron; 0.8 V; 5.6 GHz; 79 muW; CMOS frequency divider; SOS-CMOS technology; UNII band; compensation circuit; controllable delay element; digital logic; process compensation; process tolerance; ring oscillator divider calibration; temperature tolerant operation; voltage controlled ring oscillator; CMOS process; CMOS technology; Circuits; Frequency conversion; Frequency modulation; Ring oscillators; Robustness; Temperature; Voltage control; Voltage-controlled oscillators; Controllable delay element (CDE); frequency divider; process compensation;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2006.889741

Filename

4155063