Title :
On the design of combinational totally self-checking 1-out-of-3 code checkers
Author :
Lo, Jien-Chung ; Thanawastien, Suchai
Author_Institution :
Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
fDate :
3/1/1990 12:00:00 AM
Abstract :
The authors present the design of an 11-transistor combinational NMOS 1-out-of-3 code checker. The checker is totally self-checking (TSC) with respect to 36 faults out of a total of 58 faults defined at the NMOS switch and layout geometrical levels, and achieves the TSC goal of a checker for most of the fault sequences. The minimum fault sequences under which the TSC goal is lost are composed of at least three faults. This might be considered as a sufficient level of safety for some implementations
Keywords :
MOS integrated circuits; automatic testing; integrated logic circuits; logic design; logic testing; NMOS; TSC goal; combinational totally self-checking 1-out-of-3 code checkers; fault sequences; minimum fault sequences; Circuit faults; Computer architecture; Delay; MOS devices; Memory management; Parallel processing; Predictive models; State-space methods; Switches; Upper bound;
Journal_Title :
Computers, IEEE Transactions on
