Title :
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling
Author :
Fujiyoshi, Toshihide ; Shiratake, Shinichiro ; Nomura, Shuou ; Nishikawa, Tsuyoshi ; Kitasho, Yoshiyuki ; Arakida, Hideho ; Okuda, Yuji ; Tsuboi, Yoshiro ; Hamada, Mototsugu ; Hara, Hiroyuki ; Fujita, Tetsuya ; Hatori, Fumitoshi ; Shimazawa, Takayoshi ; Y
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously.
Keywords :
large scale integration; low-power electronics; speech codecs; video codecs; video signal processing; voltage control; 63 mW; H.264; MPEG-4; application specific integrated circuits; audio codec LSI; clock gating; dynamic deskewing system; dynamic voltage-frequency scaling architecture; embedded DRAM; low power techniques; mobile applications; on chip voltage regulator; signal processing; slew rate control; terrestrial digital broadcasting system; visual codec LSI; voltage control; Codecs; Communication standards; Data communication; Digital audio broadcasting; Digital multimedia broadcasting; Dynamic voltage scaling; Frequency; Large scale integration; MPEG 4 Standard; Multiplexing; Application-specific integrated circuits; clock control; signal processing; video codecs; voltage control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.859337
