Title :
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
Author :
Zhang, Kevin ; Bhattacharya, Uddalak ; Chen, Zhanping ; Hamzaoglu, Fatih ; Murray, Daniel ; Vallepalli, Narendra ; Wang, Yih ; Zheng, Bo ; Bohr, Mark
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.
Keywords :
CMOS memory circuits; SRAM chips; circuit optimisation; integrated circuit design; microwave integrated circuits; power supply circuits; 1.1 V; 3 GHz; 65 nm; 70 Mbit; CMOS technology; SRAM cell array; high-frequency SRAM design; integrated column-based dynamic power supply; read operations; static random-access memory; write operations; CMOS technology; Design optimization; Energy consumption; Frequency synchronization; Integrated circuit noise; Power supplies; Random access memory; Silicon; Stability; Threshold voltage; Dynamic power supply; MOS memory integrated circuits; SRAM cell; static noise margin (SNM); static random-access memory (SRAM); write margin;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.859025
