Title :
A hybrid analog and digital VLSI neural network for intracardiac morphology classification
Author :
Coggins, Richard ; Jabri, Marwan ; Flower, Barry ; Pickard, Stephen
Author_Institution :
Syst. Eng. & Design Autom. Lab., Sydney Univ., NSW, Australia
fDate :
5/1/1995 12:00:00 AM
Abstract :
Current Implantable Cardioverter Defibrillators (ICD´s) use timing based decision trees for cardiac arrhythmia classification. Timing alone does not distinguish all rhythms for all patients. Hence, more computationally intensive morphology analysis is required for complete diagnosis. An analog VLSI neural network has been designed and tested to perform cardiac morphology classification tasks. Analog techniques were chosen to meet the strict power and area requirements of the implantable system while incurring the design difficulties of noise, drift and offsets inherent in analog approaches. The robustness of the neural network architecture however, to a large extent, overcomes these inherent shortcomings of the analog approach. The network is a 10:6:3 multilayer perceptron with on chip digital weight storage. The chip also includes a bucket brigade input to feed the Intracardiac Electrogram (ICEG) to the network and a Winner Take All circuit for converting classifications to a binary representation. The training system trained the network in loop and included a commercial implantable defibrillator in the signal processing path. The system has successfully distinguished two arrhythmia classes on a morphological basis for seven different patients with an average of 95% true positive and 97% true negative detections for the dangerous rhythm. The chip was implemented in 1.2 μm CMOS and consumes less than 200 nW maximum average power from a 3 V supply in an area of 2.2×2.2 mm2
Keywords :
CMOS integrated circuits; VLSI; defibrillators; electrocardiography; medical signal processing; mixed analogue-digital integrated circuits; multilayer perceptrons; neural chips; patient monitoring; pattern classification; 1.2 micron; 200 nW; 3 V; CMOS chip; bucket brigade input; cardiac arrhythmia classification; current implantable cardioverter defibrillators; hybrid analog/digital VLSI neural network; intracardiac electrogram; intracardiac morphology classification; morphology analysis; multilayer perceptron; onchip digital weight storage; timing based decision trees; winner take all circuit; Cardiology; Classification tree analysis; Decision trees; Morphology; Neural networks; Performance evaluation; Rhythm; Testing; Timing; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of