Title :
10 GB/s bit-synchronizer circuit with automatic timing alignment by clock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs
Author :
Wennekers, Peter ; Novotny, Ulrich ; Huelsmann, Axel ; Kaufel, Gudrun ; Koehler, Klaus ; Raynor, Brian ; Schneider, Joachim
Author_Institution :
Fraunhofer Inst. for Appl. Solid State Phys., Freiburg, Germany
fDate :
10/1/1992 12:00:00 AM
Abstract :
A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are ±54° relative to the `in bit cell center´ position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 μm recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V
Keywords :
III-V semiconductors; aluminium compounds; field effect integrated circuits; flip-flops; gallium arsenide; integrated logic circuits; optical communication equipment; optical receivers; phase comparators; synchronisation; 0.3 micron; 1.9 V; 10 Gbit/s; 1010-bit sequence; 230 mW; AlGaAs-GaAs-AlGaAs quantum well technology; EXCLUSIVE-OR gates; active signal splitter; automatic timing alignment; bit-synchronizer circuit; clock phase shifting; data sampling; data transition detection; enhancement depletion quantum well FET process; in bit cell centre position; master-slave flip -flops; monotonous phase comparison; optical data receivers; phase comparator circuit; power dissipation; supply voltage; Bit rate; Circuits; Clocks; Gain measurement; Master-slave; Phase detection; Phase measurement; Sampling methods; Signal sampling; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
