Title :
A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects
Author :
Schinkel, Daniël ; Mensink, Eisse ; Klumperink, Eric A M ; Van Tuijl, Ed A J M ; Nauta, Bram
Author_Institution :
IC-Design Group, Univ. of Twente, Enschede, Netherlands
Abstract :
Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but the classical repeater insertion approach requires a large number of repeaters while the intrinsic data capacity of each interconnect-segment is only partially used. In this paper we analyze interconnects and show how a combination of layout, termination and equalization techniques can significantly increase the data rate for a given length of uninterrupted interconnect. To validate these techniques, a bus-transceiver test chip in a 0.13-μm, 1.2-V, 6-M copper CMOS process has been designed. The chip uses 10-mm-long differential interconnects with wire widths and spacing of only 0.4 μm. Differential interconnects are insensitive to common-mode disturbances (e.g., non-neighbor crosstalk) and enable the use of twists to mitigate neighbor-to-neighbor crosstalk. With transceivers operating in conventional mode, the chip achieves only 0.55 Gb/s/ch. The achievable data rate increases to 3 Gb/s/ch (consuming 2 pJ/bit) with a pulse-width pre-emphasis technique, used in combination with resistive termination.
Keywords :
digital integrated circuits; integrated circuit interconnections; system buses; transceivers; 0.13 micron; 0.4 micron; 1.2 V; 10 mm; 3 Gbit/s; ISI; RC-limited interconnects; bus-transceiver; crosstalk mitigation; data bus; differential interconnects; duty cycle; equalization techniques; intersymbol interference; layout technique; on-chip communication; on-chip interconnects; pulse-width pre-emphasis technique; repeater insertion approach; resistive termination; termination technique; transceiver; uninterrupted interconnect; Bandwidth; Bridges; CMOS process; Copper; Crosstalk; Data communication; Process design; Repeaters; Testing; Transceivers; Crosstalk; data bus; duty cycle; interconnect; intersymbol interference (ISI); on-chip communication; pre-emphasis; pulse-width; repeater insertion; transceivers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.859880