DocumentCode
777680
Title
A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results
Author
Calin, T. ; Vargas, F. ; Nicolaidis, M. ; Velazco, R.
Author_Institution
TIMA/INPG Lab., Grenoble, France
Volume
42
Issue
6
fYear
1995
fDate
12/1/1995 12:00:00 AM
Firstpage
1592
Lastpage
1598
Abstract
This paper presents the architecture of a CMOS static RAM which is tolerant to radiation-induced upsets. It employs transient current sensing circuits to achieve concurrent, event-driven SEU detection and correction. Tests with simulated upsets and preliminary radiation tests showed the detection of all upsets and proved the effectiveness of the approach
Keywords
CMOS memory circuits; SRAM chips; error correction; error detection; integrated circuit reliability; integrated circuit testing; radiation hardening (electronics); transient response; CMOS static RAM; SEU correction; SEU-tolerant SRAM; concurrent detection/correction; event-driven SEU detection; low-cost highly reliable SRAM; radiation tests; radiation tolerant memory chip; radiation-induced upsets; transient current sensing circuits; Circuit testing; Delay; Error correction; Monitoring; Power dissipation; Prototypes; Random access memory; Read-write memory; Single event upset; Transient analysis;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/23.488754
Filename
488754
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