Title :
Evaluation of the upset risk in CMOS SRAM through full three dimensional simulation
Author :
Moreau, Yves ; Duzellier, Sophie ; Asiot, Jeang
Author_Institution :
Centre d´´Electron. de Montpellier, France
fDate :
12/1/1995 12:00:00 AM
Abstract :
Upsets caused by incident heavy ions on CMOS static RAMs are studied. Three dimensional device simulations, based on a description of a full epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular influences of hit location and incidence angle are examined
Keywords :
CMOS memory circuits; SRAM chips; circuit analysis computing; ion beam effects; CMOS SRAM; CMOS static RAM; charge collection mechanisms; epitaxial CMOS inverter; hit location; incidence angle; incident heavy ions; multiple bit error risk; single bit error risk; three dimensional simulation; upset risk; Circuit simulation; Electrodes; Equations; Finite element methods; Medical simulation; Packaging; Pulse generation; Random access memory; Solid modeling; Space technology;
Journal_Title :
Nuclear Science, IEEE Transactions on
