DocumentCode :
778302
Title :
A new direct design for three-input XOR function on the transistor level
Author :
Fang, Sung-Chuan ; Wang, Jyh-Ming ; Feng, Wu-Shiung
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
43
Issue :
4
fYear :
1996
fDate :
4/1/1996 12:00:00 AM
Firstpage :
343
Lastpage :
348
Abstract :
Instead of cascading two two-input XOR gates, we design a new structure of three-input function on the transistor level in this paper. The basic structure of the proposed three-input XOR function utilizes the least number of transistors and no complementary input signals are needed. From the simulated results, it proves the basic structure works very well. Under the consideration of driving capacity, we can simply attach a standard buffer to the basic structure for this purpose. The experiments verify that our driving-enhanced three-input XOR gate has more driving capacity and less power consumption as well as power-delay product than the previous cascaded designs using the same number of transistors. The simulation work is done by HSPICE on a SUN SPARC10 workstation
Keywords :
SPICE; buffer circuits; logic CAD; multivalued logic circuits; HSPICE; driving capacity; power consumption; power-delay product; standard buffer; three-input XOR function; transistor level; Adders; Circuits; Control systems; Error correction codes; Field programmable gate arrays; Frequency synthesizers; Phase locked loops; Prototypes; Servomotors; Variable structure systems;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7122
Type :
jour
DOI :
10.1109/81.488816
Filename :
488816
Link To Document :
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