Title :
Open faults in BiCMOS gates
Author :
Ma, Siyad C. ; McCluskey, Edward J.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
fDate :
5/1/1995 12:00:00 AM
Abstract :
Opens in BiCMOS structures are analyzed here. It is shown that some opens cannot be detected by stuck-fault or other functional tests, since some transistors in BiCMOS gates do not affect the logical function of the gate. A switch-level model for CMOS circuits is extended to include bipolar devices. With this switch-level model, opens that cannot be detected by stuck-faults or other functional tests are easily identified. It is also shown that, in BiCMOS circuits, an open defect in one transistor can accelerate the wearout of another nondefective transistor
Keywords :
BiCMOS digital integrated circuits; BiCMOS logic circuits; fault diagnosis; integrated circuit testing; logic gates; logic testing; BiCMOS gates; bipolar devices; open faults; switch-level model; transistors; Acceleration; BiCMOS integrated circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Logic testing; MOSFETs; Semiconductor device modeling; Switching circuits;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
