• DocumentCode
    779100
  • Title

    Low latency time CORDIC algorithms

  • Author

    Timmermann, Dirk ; Hahn, Helmut ; Hosticka, Bedrich J.

  • Author_Institution
    Fraunhofer Inst. of Microelectron. Circuits & Syst., Duisburg, Germany
  • Volume
    41
  • Issue
    8
  • fYear
    1992
  • fDate
    8/1/1992 12:00:00 AM
  • Firstpage
    1010
  • Lastpage
    1015
  • Abstract
    Several methods for increasing the speed of the CORDIC algorithm are presented. First, an improved method which guarantees a constant scale factor when employing redundant addition schemes is developed. Then, an architecture with increased parallelism which considerably reduces the CORDIC latency time and the amount of hardware is described
  • Keywords
    adders; computational complexity; digital arithmetic; iterative methods; number theory; CORDIC algorithms; constant scale factor; latency time; parallel architecture; redundant addition; Adders; Computer architecture; Delay; Digital arithmetic; Equations; Hardware; Helium; Iterative algorithms; Parallel processing; Vectors;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.156543
  • Filename
    156543
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=779100