A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit

A novel concept and structure for a high-speed time division switch operating in the gigabit/second range are presented. The basic concept is to use the high-speed memory in the time switch effectively by means of a slow writing/fast reading method. numbers of speech data are written in parallel during clock times and read serially during one clock time for one switched datum. By using the concept and high-speed memories that we have, a data switching system which approaches the memory and read cycle limit can be realized with a proper time margin.