Title :
Multiply-by-two gain stage with reduced mismatch sensitivity
Author :
Zare-Hoseini, H. ; Shoaei, O. ; Kale, I.
Author_Institution :
Appl. DSP & VLSI Res. Group, Univ. of Westminster, London, UK
fDate :
3/17/2005 12:00:00 AM
Abstract :
A new multiply-by-two gain stage is presented, suppressing the gain sensitivity to capacitor mismatches. Using one operational amplifier in three phases, a gain of two, which is not highly influenced by the mismatches between the capacitors, is achieved. Circuit-level Monte-Carlo simulations support the reduction of matching requirements.
Keywords :
Monte Carlo methods; amplification; circuit simulation; differential amplifiers; operational amplifiers; voltage multipliers; CMOS; capacitor mismatch sensitivity reduction; circuit-level Monte-Carlo simulations; fully differential opamp; multiply-by-two gain stage; operational amplifier;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20057190
