DocumentCode
779984
Title
Multiply-by-two gain stage with reduced mismatch sensitivity
Author
Zare-Hoseini, H. ; Shoaei, O. ; Kale, I.
Author_Institution
Appl. DSP & VLSI Res. Group, Univ. of Westminster, London, UK
Volume
41
Issue
6
fYear
2005
fDate
3/17/2005 12:00:00 AM
Firstpage
289
Lastpage
290
Abstract
A new multiply-by-two gain stage is presented, suppressing the gain sensitivity to capacitor mismatches. Using one operational amplifier in three phases, a gain of two, which is not highly influenced by the mismatches between the capacitors, is achieved. Circuit-level Monte-Carlo simulations support the reduction of matching requirements.
Keywords
Monte Carlo methods; amplification; circuit simulation; differential amplifiers; operational amplifiers; voltage multipliers; CMOS; capacitor mismatch sensitivity reduction; circuit-level Monte-Carlo simulations; fully differential opamp; multiply-by-two gain stage; operational amplifier;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20057190
Filename
1421152
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