Title :
InTeRail: a test architecture for core-based SOCs
Author :
Kagaris, Dimitri ; Tragoudas, Spyros ; Kuriakose, Sherin
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
A flexible test architecture for embedded cores and all interconnects in a system-on chip (SOC) is presented. It targets core testing parallelism and reduced test application time by using, as much as possible, existing core interconnects to form TAM paths. It also provides for dynamic wrapper reconfiguration. Algorithms that minimize the use of extra interconnects for the TAM path formation are presented and evaluated.
Keywords :
computer architecture; design for testability; embedded systems; system-on-chip; core testing parallelism; design for testability; dynamic wrapper reconfiguration; embedded core; system-on chip; test access mechanism; test architecture; Circuit testing; Design for testability; Design methodology; Hardware; Integrated circuit interconnections; Pins; Rails; Routing; System testing; Time to market; Index Terms- System-on-chip test; cores; design for testability.; test access mechanism;
Journal_Title :
Computers, IEEE Transactions on
