A 3x blind ADC-based CDR for a 20 dB loss channel

Author

Jalali, Mohammad Sadegh ; Ting, Clifford ; Liang, Joshua ; Sheikholeslami, Ali ; Kibune, Masaya ; Tamura, Hirotaka

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada

Volume

62

Issue

6

fYear

2015

fDate

Jun-15

Firstpage

1658

Lastpage

1667

Abstract

This paper proposes using a 3-bit ADC to blindly sample the received data from a channel with 20 dB loss at Nyquist at 3× the baud rate. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our test chip fabricated in Fujitsu\´s 65 nm CMOS show a high frequency jitter tolerance of 0.25 UIpp for a 5 Gb/s PRBS31 with a 60" FR4 channel.

Keywords

CMOS integrated circuits; analogue-digital conversion; clock and data recovery circuits; FR4 channel; Fujitsu CMOS; PRBS31; analog-to-digital converter; bit rate 5 Gbit/s; blind ADC-based CDR; clock and data recovery circuits; high frequency jitter tolerance; loss channel; power consumption; size 65 nm; word length 5 bit to 3 bit; Clocks; Decision feedback equalizers; Interpolation; Jitter; Power demand; Receivers; ADC-based CDR; blind-sampling CDR; clock and data recovery; feed-forward CDR;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2015.2418839

Filename

7112581