Title :
Heterogeneous integration of OE arrays with Si electronics and microoptics
Author_Institution :
Honeywell VCSEL Opt. Products, Plymouth, MN, USA
fDate :
2/1/2002 12:00:00 AM
Abstract :
This paper describes recent developments of the smart pixel array (SPA) technology for massively parallel optical interconnect applications. Built on Honeywell´s commercially successful 850 nm vertical cavity surface emitting laser (VCSEL) technology, the SPA employs a 2D array of VCSELs and photodetectors (PDs). It aims to push optical interconnect density and capacity to a new level, which brings chip-level input and output (I/O) capacity to the order of 100s to 1000s of gigabit per second (Gbps). This technology has several unique features that make it not only technically feasible but also practical for low cost manufacturing. First, it employs an optoelectronic (OE) array based on the new generation of oxide-confined VCSELs that have desired characteristics such as very high speed, high efficiency, and good array uniformity. Second, the OE array has monolithically integrated VCSELs and PDs that provides true bi-directional optical I/O solutions at the chip-scale. Third, it uses hybrid integration techniques such as solder bump bonding and wafer scale integration. The 2D arrays of VCSELs and PDs can be seamlessly integrated with a beam shaping micro-optics array, and with the state-of-the-art Si-based VLSI electronic ICs. Last, and perhaps most importantly, all of the technology implementations follow the guideline of being compatible with mainstream low cost manufacturing practices. Device performance characteristics, integration approach, and prototype demonstration SPA technology up to over 1000 I/O channels per chip are presented, including some early system prototype demonstrations. We believe the SPA technology provides future application specific integrated circuits (ASICs) with new form packaging solutions-a solution that give an ASIC with unprecedented large capacity of very high density and high speed I/Os. It can be used as a new building block to implement varieties of system architectures that are not possible to build with current electrical interconnection
Keywords :
integrated circuit interconnections; integrated optoelectronics; laser cavity resonators; micro-optics; optical arrays; optical interconnections; parallel architectures; photodetectors; semiconductor lasers; smart pixels; soldering; surface emitting lasers; 2D VCSEL/photodetector array; 850 nm; ASIC; OE arrays; Si; Si electronics; VCSEL; VLSI; application specific integrated circuits; array uniformity; beam shaping micro-optics array; chip I/O channels; chip-level input/output capacity; chip-scale bi-directional optical I/O; electrical interconnection; heterogeneous integration; hybrid integration techniques; integration approach; manufacturing practices; massively parallel optical interconnect applications; micro-optics; monolithically integrated PDs; monolithically integrated VCSELs; optical interconnect capacity; optical interconnect density; optoelectronic array; oxide-confined VCSELs; packaging form; performance characteristics; prototype SPA technology; smart pixel array technology; solder bump bonding; system architectures; technology implementations; vertical cavity surface emitting lasers; wafer scale integration; Application specific integrated circuits; Costs; Integrated circuit technology; Manufacturing; Optical arrays; Optical interconnections; Prototypes; Smart pixels; Surface emitting lasers; Vertical cavity surface emitting lasers;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/TADVP.2002.1017684