Power-aware test planning in the early system-on-chip design exploration process

Test application and test design, performed to ensure the production of fault-free chips, are becoming complicated and very expensive, especially in the case of SoCs (system-on-chip), as the number of possible faults in a chip is increasing dramatically due to the technology development. It is therefore important to take test design into consideration as early as possible in the SoC design-flow in order to develop an efficient test solution. We propose a technique for modular core-based SoCs where test design is integrated in the early design exploration process. The technique can, in contrast to previous approaches, already be used in the core selection process to evaluate the impact on the system´s final test solution imposed by different design decisions. The proposed technique considers the interdependent problems of core selection, test scheduling, TAM (test access mechanism) design, test set selection, and test resource floorplanning, and minimizes a weighted cost-function based on test time and TAM routing cost, while considering test conflicts and test power limitations. Concurrent scheduling of tests is used to minimize the test application time; however, concurrent test application leads to higher activity during the testing and, hence, higher power consumption. The power consumed during testing is, in general, higher than that during normal operation since it is desirable with hyperactivity in order to maximize the number of tested faults in a minimal time. A system under test can actually be damaged during testing and, therefore, power constraints must be considered. However, power consumption is complicated to model and, often, simplistic models that focus on the global system power limit only have been proposed and used. We therefore include a novel three-level power model: system, power-grid, and core.