DocumentCode :
780312
Title :
Bit-parallel finite field multiplier and squarer using polynomial basis
Author :
Wu, Huapeng
Author_Institution :
Dept. of Combinatorics & Optimization, Waterloo Univ., Ont., Canada
Volume :
51
Issue :
7
fYear :
2002
fDate :
7/1/2002 12:00:00 AM
Firstpage :
750
Lastpage :
758
Abstract :
Bit-parallel finite field multiplication using polynomial basis can be realized in two steps: polynomial multiplication and reduction modulo the irreducible polynomial. In this article, we present an upper complexity bound for the modular polynomial reduction. When the field is generated with an irreducible trinomial, closed form expressions for the coefficients of the product are derived in term of the coefficients of the multiplicands. The complexity of the multiplier architectures and their critical path length are evaluated, and they are comparable to the previous proposals for the same class of fields. An analytical form for bit-parallel squaring operation is also presented. The complexities for bit-parallel squarer are also derived when an irreducible trinomial is used. Consequently, it is argued that to solve multiplicative inverse using polynomial basis can be at least as good as using a normal basis
Keywords :
computational complexity; cryptography; parallel algorithms; polynomials; bit-parallel algorithms; bit-parallel finite field multiplication; bit-parallel squaring; closed form expressions; complexity bound; critical path length; cryptography; finite fields arithmetic; hardware architecture; polynomial basis; polynomial multiplication; Communication networks; Computer architecture; Computer networks; Digital arithmetic; Elliptic curve cryptography; Galois fields; Hardware; Helium; Polynomials; Proposals;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2002.1017695
Filename :
1017695
Link To Document :
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