DocumentCode :
780680
Title :
Single-event gate-rupture in power MOSFETs: prediction of breakdown biases and evaluation of oxide thickness dependence
Author :
Allenspach, M. ; Mouret, I. ; Titus, J.L. ; Wheatley, C.F., Jr. ; Pease, R.L. ; Brews, J.R. ; Schrimpf, R.D. ; Galloway, K.F.
Author_Institution :
Arizona Univ., Tucson, AZ, USA
Volume :
42
Issue :
6
fYear :
1995
Firstpage :
1922
Lastpage :
1927
Abstract :
Single-Event Gate-Rupture (SEGR) in Vertical Double Diffused Metal-Oxide Semiconductor (VDMOS) power transistors exposed to a given heavy ion LET occurs at a critical gate bias that depends on the applied drain bias. A method of predicting the critical gate bias for non-zero drain biases is presented. The method requires as input the critical gate bias vs. LET for V DS=0V. The method also predicts SEGR sensitivity to improve for larger gate-oxide thicknesses. All predictions show agreement with experimental test data.
Keywords :
electric breakdown; ion beam effects; power MOSFET; VDMOS transistor; breakdown bias; heavy ion LET; oxide thickness; power MOSFETs; single-event gate-rupture; Charge carrier processes; Computational modeling; Electrons; Geometry; Neck; Predictive models; Silicon; Slabs; Solid modeling; Testing;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/23.489234
Filename :
489234
Link To Document :
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