Design of an efficient CORDIC-based architecture for synchronization in OFDM

This paper presents a new architecture to estimate the time and frequency offsets required to synchronize packed-based orthogonal frequency division multiplexing (OFDM) modulation receivers. The proposed estimators, which operate in the frequency-domain, use CORDIC (coordinate rotation digital computer) processors to achieve an efficient hardware implementation which is simpler than other computational intensive estimators based on processing in the time-domain. The hardware saving is twofold: the proposed implementation does not require complex cells such as multipliers or dividers; and some cells already existing in OFDM receivers for pay-load demodulation are reused during the synchronization phase. In addition, this paper also shows how to optimize the CORDIC cells, in terms of number of iterations, to provide a given signal-to-noise ratio (SNR) due to approximation error, and proposes an error propagation model for the proposed synchronization architecture