Title :
IDDQ design and test advantages propel industry
Author :
Hawkins, Charles F. ; Soden, Jerry M.
Author_Institution :
New Mexico Univ., Albuquerque, NM, USA
Abstract :
The IDDQ test method measures the quiescent power supply current of CMOS ICs for select test vectors, or logic states, and provides a clear indication of defects, failure mechanisms, and many types of design errors. Underlying this type of test are design principles that inherently provide high defect coverage, as well as diagnosis capability and physical localization. The ability of IDDQ testing to rapidly gauge an IC\´s health is like a nurse taking a patient\´s temperature. This is an especially appropriate analogy because it underscores that IDDQ testing is not a panacea. As with a patient, other "vital signs" are needed. The authors give a unique perspective into the design of a submicron-technology microprocessor (approximately 1 million transistor, 1OO MHz-plus design). Stringent testability and quality goals drove their selection of IDDQ testing in addition to at-speed functional testing, boundary scan, internal scan, and built-in self-test. They demonstrate the many benefits of IDDQ testing, including substantially reduced power consumption and the ability to merge readily with other testability and high-performance goals
Keywords :
CMOS integrated circuits; computer testing; integrated circuit testing; logic testing; CMOS ICs; IDDQ test method; at-speed functional testing; boundary scan; built-in self-test; defect coverage; design errors; diagnosis capability; high-performance goals; internal scan; logic states; physical localization; quiescent power supply current; reduced power consumption; submicron-technology microprocessor; testability; Automatic testing; CMOS logic circuits; Current measurement; Current supplies; Failure analysis; Logic design; Logic testing; Power measurement; Power supplies; Temperature;
Journal_Title :
Design & Test of Computers, IEEE
