Source and Drain Series Resistance Reduction for N-Channel Transistors Using Solid Antimony (Sb) Segregation (SSbS) During Silicidation

Author

Wong, Hoong-Shing ; Koh, Alvin Tian-Yi ; Chin, Hock-Chun ; Chan, Lap ; Samudra, Ganesh ; Yeo, Yee-Chia

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore

Volume

29

Issue

7

fYear

2008

fDate

7/1/2008 12:00:00 AM

Firstpage

756

Lastpage

758

Abstract

We report the first integration of a novel solid antimony (Sb) segregation (SSbS) process in a transistor fabrication flow. A thin solid Sb layer, which acts as a large source of n-type dopants, was deposited beneath a metallic nickel layer prior to source-drain silicidation. Following nickel silicidation, a very high concentration of Sb was incorporated at the NiSi/Si interface. The SSbS process is demonstrated to reduce the effective Schottky barrier (SB) height and parasitic series resistance in an n-channel field-effect transistor, leading to enhanced drive current performance without degradation in the OFF -state leakage current. Performance enhancement is also maintained when the supply voltage is reduced from 1.3 to 0.8 V.

Keywords

MOSFET; antimony; leakage currents; nickel compounds; segregation; silicon; N-MOS device; NiSi-Si; OFF-state leakage current; Sb; Schottky barrier height reduction; drain series resistance reduction; metallic nickel layer; n-channel field-effect transistor; n-type dopants; nickel silicidation; solid antimony segregation process; source series resistance reduction; source-drain silicidation; voltage 1.3 V to 0.8 V; Amplitude modulation; Degradation; FETs; Fabrication; Leakage current; Nickel; Schottky barriers; Silicidation; Solids; Voltage; Antimony segregation; Schottky barrier (SB); parasitic series resistance; salicidation;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2008.923712

Filename

4558125