Algorithmic and architectural co-design for integer motion estimation of AVS

The video part of A VS has been finalized, in order to enhance coding performance. AVS video standard adopts some new features for motion estimation, such as variable block size search, multiple reference frames, and motion vector prediction. However, the better performance comes at the price of high computational complexity, data dependence and memory access requirement. These new features also make the hardware implementation more difficult, especially for real-time applications. In this paper, we firstly propose an integer motion estimation algorithm from hardware-oriented viewpoint. Experimental results show that the proposed algorithm has almost the same performance as the reference software of AVS in SDTV applications. Then the corresponding VLSI architecture is presented. The VLSI architecture has been described in Verilog HDL and synthesized using 0.18 mum Artisan CMOS cells library. The circuit totally costs about 400 K equivalent logic gates. At 108 MHz working frequency, the circuit can meet the real-time requirement for SDTV (720times576, 25 fps) applications, with the search area of 192times192. The co-design obtains better tradeoff between performance and gate-count