Title :
Architectural power analysis: The dual bit type method
Author :
Landman, Paul E. ; Rabaey, Jan M.
Author_Institution :
Integrated Syst. Lab., Texas Instrum. Inc., Dallas, TX, USA
fDate :
6/1/1995 12:00:00 AM
Abstract :
This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies characterize modules for purely random inputs, they fail to account for the effect of signal statistics on switching activity. The dual bit type (DBT) model, however, accounts not only for the random activity of the least significant bits (LSB´s), but also for the correlated activity of the most significant bits (MSB´s), which contain two´s-complement sign information. The resulting model is parameterizable in terms of complexity factors such as word length and can be applied to a wide variety of modules ranging from adders, shifters, and multipliers to register files and memories. Since the model operates at the register transfer level (RTL), it is orders of magnitude faster than gate- or circuit-level tools, but while other architecture-level techniques often err by 50-100% or more, the DBT method offers error rates on the order of 10-15%.<>
Keywords :
VLSI; circuit analysis computing; hardware description languages; high level synthesis; logic design; table lookup; architectural power analysis; black-box models; complexity factors; datapath power consumption; digital circuits; dual bit type method; least significant bits; most significant bits; physical capacitance; register transfer level; signal statistics; switching activity; two´s-complement sign information; word length; Capacitance; Circuits; Delay estimation; Energy consumption; Power generation; Power system modeling; Process design; Registers; Semiconductor device modeling; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on