Modeling SiGe FinFETs With Thin Fin and Current-Dependent Source/Drain Resistance

Author

Khandelwal, Sourabh ; Duarte, Juan Pablo ; Medury, Aditya ; Chauhan, Yogesh S. ; Salahuddin, Sayeef ; Chenming Hu

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California at Berkeley, Berkeley, CA, USA

Volume

36

Issue

7

fYear

2015

fDate

Jul-15

Firstpage

636

Lastpage

638

Abstract

In this letter, we model future generation SiGe FinFETs using the industry standard compact model BSIM-CMG. BSIM-CMG is enhanced to model these aggressively scaled devices. It is found that in these narrow fin (fin width W_fin = 12 nm) devices spacer region resistance behaves nonlinearly with drain-current. This nonlinear resistance behavior arises due to the saturation of carrier velocity in the spacer region. Accurate modeling of spacer region nonlinearity is important to predict the drain-current and the device transconductance. The developed model captures this phenomenon very well and produces excellent agreement with experimental data.

Keywords

MOSFET; electric resistance; silicon compounds; BSIM-CMG; FinFET; SiGe; carrier velocity saturation; current-dependent source-drain resistance; device transconductance; industry standard compact model; narrow fin devices spacer region resistance; nonlinear resistance behavior; thin fin; FinFETs; Integrated circuit modeling; Logic gates; Resistance; Semiconductor device modeling; Silicon germanium; Standards; BSIM-CMG; Compact Model; FinFETs; Silicon Germanium (SiGe); Silicon germanium (SiGe); compact model;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2015.2437794

Filename

7112615