Title :
Implementation of micropipelines in enable/disable CMOS differential logic
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
fDate :
6/1/1995 12:00:00 AM
Abstract :
This paper examines an alternative implementation of micropipeline logic/data processing structures. To satisfy the timing requirements of the micropipeline, currently a delay element needs to be introduced in each of its stages. The alternative approach presented here eliminates this by using a differential CMOS logic family-enable/disable CMOS differential logic (ECDL) instead of the conventional static CMOS. This will ease the process of synthesizing micropipeline stages. The effectiveness of this technique in eliminating the delay requirement has been exemplified by presenting an adder implemented using ECDL.<>
Keywords :
CMOS logic circuits; adders; digital arithmetic; logic design; pipeline processing; adder implementation; enable/disable CMOS differential logic; micropipelines; timing requirements; Adders; CMOS logic circuits; CMOS process; Clocks; Delay effects; Digital systems; Large-scale systems; Signal processing; Switches; Timing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
