Title :
Behavioral simulation of fractional-N frequency synthesizers and other PLL circuits
Author :
Perrott, Michael H.
Abstract :
Two techniques are presented that allow fast and accurate simulation of fractional-N synthesizers. A uniform time step allows implementation of these techniques in various simulation frameworks, such as Verilog, Matlab, and C or C++ programs. The techniques are also applicable to the simulation of other PLL systems, such as clock and data recovery circuits
Keywords :
circuit simulation; frequency synthesizers; hardware description languages; phase locked loops; C programs; C++ programs; Matlab; PLL circuits; Verilog; behavioral simulation; clock circuits; data recovery circuits; fractional-N frequency synthesizers; uniform time step; Charge pumps; Circuit simulation; Computational modeling; Frequency conversion; Frequency synthesizers; Noise figure; Phase frequency detector; Phase locked loops; Phase noise; Voltage-controlled oscillators;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2002.1018136
