• DocumentCode
    782127
  • Title

    AC scan path selection for physical debugging

  • Author

    Crouch, Alfred L. ; Potter, John C. ; Doege, Jason

  • Volume
    20
  • Issue
    5
  • fYear
    2003
  • Firstpage
    34
  • Lastpage
    40
  • Abstract
    Commercial EDA tools support critical-path identification, as well as transition and path delay ATPG. But how can you narrow down the target faults or paths, and which ATPG technique should you use? The authors present a practical methodology addressing these important questions.
  • Keywords
    automatic test pattern generation; boundary scan testing; delays; AC scan path selection; ATPG; critical-path identification; path delay; physical debugging; transition faults; Automatic test pattern generation; Debugging; Delay; Electronic design automation and methodology; Frequency; Histograms; Libraries; Process design; Testing; Timing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2003.1232254
  • Filename
    1232254
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=782127