DocumentCode :
782150
Title :
Obtaining high defect coverage for frequency-dependent defects in complex ASICs
Author :
Madge, Robert ; Benware, Brady R. ; Daasch, W. Robert
Author_Institution :
LSI Logic, Gresham, OR, USA
Volume :
20
Issue :
5
fYear :
2003
Firstpage :
46
Lastpage :
53
Abstract :
Structured delay tests have been around for years, but how effectively do they identify defective silicon, even at reduced frequency? How much overkill is associated with their use? The authors present data from industrial circuits aimed at these and other aspects of speed testing.
Keywords :
application specific integrated circuits; integrated circuit testing; logic testing; complex ASIC; defect coverage; frequency-dependent defects; industrial circuits; speed testing; structured delay tests; Application specific integrated circuits; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Delay effects; Frequency; Logic testing; Silicon; Timing;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2003.1232256
Filename :
1232256
Link To Document :
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