Abstract :
As optical link speeds get faster, demands for performance and embedded network services impose increasing flexibility demands. Internet routers must become more efficient and programmable. A new hardware architecture using a dynamic reconfigurable logic (DRL) circuit, along with its design methodology, is proposed. Our approach is to allocate all resources using the dynamic reconfigurable control switch (DRCS). The design space for scheduling the DRL for the networking application (router) is explored. Our proposal outperforms recent network processors since it has a better memory interface and because chained nodes of a thread can be executed at once. Our architecture offers an attractive alternative to expensive commercial solutions employing multiple content addressable memory (CAM) devices and application specific integrated circuits (ASICs). By providing high-performance at low per-ports costs, our architecture is a prime candidate for system-on-chip (SoC) solutions for next generation programmable router port processors.
Keywords :
electronic switching systems; integrated circuit design; integrated logic circuits; logic design; processor scheduling; reconfigurable architectures; resource allocation; system-on-chip; telecommunication network routing; ASIC; Internet routers; SoC; application specific integrated circuits; chained nodes; dynamic reconfigurable control switch; dynamic reconfigurable logic circuit; hardware architecture; memory interface; multiple content addressable memory; programmable router port processors; reconfigurable architecture; resource allocation; scalable architecture; system-on-chip; Circuits; Design methodology; Hardware; Internet; Optical fiber communication; Processor scheduling; Reconfigurable architectures; Reconfigurable logic; Resource management; Switches;
