DocumentCode :
782742
Title :
Scheme for distributing high-speed clock signals in a large digital system
Author :
Padin, S.
Author_Institution :
California Inst. of Technol., Big Pine, CA, USA
Volume :
25
Issue :
2
fYear :
1989
Firstpage :
92
Lastpage :
93
Abstract :
The details of a clock distribution circuit for a large digital system operating at 250 MHz are presented. The arrangement provides pulse compression control and preserves the clock timing at the 100 ps level even when parts of the circuit are replaced.
Keywords :
clocks; digital systems; 100 ps; 250 MHz; clock distribution circuit; clock timing; high-speed clock signals; large digital system; pulse compression control;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19890068
Filename :
14236
Link To Document :
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