• DocumentCode
    782958
  • Title

    A specification-driven architectural design environment

  • Author

    Tanir, O. ; Agarwal, Vinod K. ; Bhatt, P.C.P.

  • Author_Institution
    Bell Canada, Longueuil, Que., Canada
  • Volume
    28
  • Issue
    6
  • fYear
    1995
  • fDate
    6/1/1995 12:00:00 AM
  • Firstpage
    26
  • Lastpage
    35
  • Abstract
    We introduce an environment we´ve developed that helps designers represent, model, and explore design tradeoffs at the architectural abstraction level and synthesize designs at the behavioral level. The Design Analysis and Synthesis Environment (DASE) accomplishes this by supporting design capture, design space exploration, and validation for the final design synthesis. DASE specifically caters to design capture via the Design Specification Language (DSL) description, exploration through simulation, and behavioral synthesis through a translator that produces VHDL output for behavior synthesis. DASE has a support library for telecommunication systems, although DASE´s library support system can he reconfigured for other domains. We illustrate the various capabilities of DASE, such as specification capture, design exploration, software and hardware modeling, and synthesis. We discuss models based on Petri nets, summarize other DASE designs, and present results reflecting synthesized code sizes-the resulting executable descriptions of the hardware and software
  • Keywords
    CAD; computer architecture; formal specification; systems analysis; virtual machines; DASE; Design Analysis and Synthesis Environment; Design Specification Language; Petri nets; VHDL output; architectural abstraction level; behavior synthesis; behavioral synthesis; design capture; design space exploration; design tradeoffs; executable descriptions; final design synthesis; specification capture; specification driven architectural design environment; specification-driven architectural design environment; support library; synthesized code sizes; telecommunication systems; Circuit synthesis; DSL; Hardware; Logic arrays; Logic testing; Object oriented modeling; Programmable logic arrays; Software design; Software libraries; Time to market;
  • fLanguage
    English
  • Journal_Title
    Computer
  • Publisher
    ieee
  • ISSN
    0018-9162
  • Type

    jour

  • DOI
    10.1109/2.386983
  • Filename
    386983