Title :
A multiprocessors architecture for a HDTV motion estimation system
Author :
Hervigo, R. ; Kowalczuk, J. ; Mlynek, D.
Author_Institution :
Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
fDate :
8/1/1992 12:00:00 AM
Abstract :
A hierarchical block matching algorithm is a promising technique for motion estimation, especially in terms of computations. A real-time implementation of this algorithm was investigated for a high-definition TV data input rate. This system used a two-step hierarchical block matching algorithm. A highly parallel and pipelining multiprocessor architecture built with specific processors is described
Keywords :
high definition television; motion estimation; parallel architectures; pipeline processing; HDTV motion estimation; hierarchical block matching algorithm; high-definition TV; parallel processing; pipelining multiprocessor architecture; real-time implementation; Bit rate; Codecs; Computer architecture; Data structures; Filtering; HDTV; Laboratories; Motion estimation; Signal processing algorithms; TV;
Journal_Title :
Consumer Electronics, IEEE Transactions on
