A communication scheme for analog VLSI perceptive systems

A communication architecture tailored for analog VLSI perceptive systems is proposed. Information is generated on a transmitter array of cells each driving a pulse generator. The resulting pulse-frequency modulated signals are transmitted through the nonarbitered, asynchronous access of pulses to a common bus. Pulses are decoded and accumulated in a receiver chip and the mapping of the activity distribution of the transmitter onto the receiver is achieved. One possible implementation of these principles is presented. The circuit description of all blocks is given and experimental results are shown: they satisfactorily support the theoretical basis upon which the system was constructed. Extensions to the communication architecture are finally presented