A Novel Digital Duty-Cycle Modulation Scheme for FPGA-Based Digital-to-Analog Conversion

Author

Lonla Moffo, Bertrand ; Mbihi, Jean

Author_Institution

Electr., Electron., Autom. & Telecommun. (EEAT) Res. Lab., Univ. of Douala, Douala, Cameroon

Volume

62

Issue

6

fYear

2015

fDate

Jun-15

Firstpage

543

Lastpage

547

Abstract

In this brief, a novel digital duty-cycle modulation (DDCM) scheme is outlined. The digital part, embedded in a field-programmable gate array (FPGA) chip, consists of a lookup DDCM map, a dual DDCM counting logic with interrupt service routines, and a holder. It is used as a building core of a well-tested 10-12 bits FPGA-based digital-to-analog converter (DAC). Experimental tests show that for a digital input bandwidth of 3 kHZ, the new DDDM technique for DAC achieves 40 dBc of surpious free dynamic range and 60 dB of NOISE FLOOR range. This performance is a challenge compared with most low cost oversampling DACs schemes with single decimation stage.

Keywords

counting circuits; digital-analogue conversion; field programmable gate arrays; DDCM scheme; FPGA chip; FPGA-based DAC; FPGA-based digital-to-analog converter; bandwidth 3 kHz; digital duty-cycle modulation scheme; dual DDCM counting logic; field-programmable gate array chip; holder; interrupt service routines; lookup DDCM map; word length 10 bit to 12 bit; Bandwidth; Clocks; Digital signal processing; Field programmable gate arrays; Pulse width modulation; Analog filter; DDCM; DDCM Data map; Dual counting logic; FPGA-based DAC; Interrupt service routines; digital duty cycle modulation (DDCM) data map; dual counting logic; field-programmable gate array (FPGA)-based digital-to-analog converter (DAC); interrupt service routines (ISR);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2015.2407233

Filename

7047825