Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I. theoretical derivation

Author

Ker, Ming-Dou ; Wu, Chung-Yu

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

42

Issue

6

fYear

1995

fDate

6/1/1995 12:00:00 AM

Firstpage

1141

Lastpage

1148

Abstract

A novel method to characterize the mechanism of positive-feedback regeneration in a p-n-p-n structure during CMOS latchup transition is developed. It is based on the derived time-varying transient poles in large-signal base-emitter voltages of the lumped equivalent circuit of a p-n-p-n structure. Through calculating the time-varying transient poles during CMOS latchup transition, if is found that there exists a transient pole to change from negative to positive and then this pole changes to negative again. A p-n-p-n structure, which has a stronger positive-feedback regeneration during turn-on transition, will lead to a larger positive transient pole. The time when the positive transient pole occurs during CMOS latchup transition is the time when the positive-feedback regeneration starts. By this positive transient pole, the positive-feedback regenerative process of CMOS latchup can be quantitatively characterized

Keywords

CMOS integrated circuits; equivalent circuits; fault currents; feedback; integrated circuit modelling; integrated circuit reliability; CMOS latchup; latchup transition; lumped equivalent circuit; p-n-p-n structure; positive transient pole method; positive-feedback regenerative process; time-varying transient poles; CMOS process; CMOS technology; Equivalent circuits; Impedance; Microelectronics; Parasitic capacitance; Power supplies; Semiconductor device modeling; Transconductance; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.387249

Filename

387249