A low-power highly linear cascoded multiple-gated transistor CMOS RF amplifier with 10 dB IP3 improvement (Revised)

A low-power highly linear CMOS RF amplifier circuit composed of a Multiple-Gated common-source FET TRansistor (MGTR) in cascode configuration is reported. In an MGTR amplifier, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/" of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/\´ and harmonic feedback, which can greatly be reduced by the cascoding MGTR output. IP3 improvement as large as 10 dB has been obtained from an experimental RF amplifier designed at 900 MHz and fabricated using 0.35 μm BiCMOS technology using only CMOS at a similar power consumption and gain as those obtainable from conventional cascode single gate transistor amplifiers.