DocumentCode :
78481
Title :
SAT-Based Analysis of Sensitizable Paths
Author :
Sauer, Matthias ; Czutro, Alexander ; Schubert, Tobias ; Hillebrecht, Stefan ; Polian, Ilia ; Becker, Bernd
Author_Institution :
Univ. of Freiburg, Freiburg, Germany
Volume :
30
Issue :
4
fYear :
2013
fDate :
Aug. 2013
Firstpage :
81
Lastpage :
88
Abstract :
A common trend in the past has been to detect delay defects in nanoscale technologies through the longest sensitisable paths. This approach does not hold up for non-trivial defects due to modeling inaccuracies. This article supports tests through all paths of customized length, using current SATsolving advances.
Keywords :
computability; SAT-based analysis; SATsolving advances; delay defects detection; nanoscale technologies; nontrivial defects; sensitisable paths; Circuit faults; Encoding; Integrated circuit modeling; Logic gates; Manufacturing processes; Nanoscale devices; Sensitivity; Timing;
fLanguage :
English
Journal_Title :
Design & Test, IEEE
Publisher :
ieee
ISSN :
2168-2356
Type :
jour
DOI :
10.1109/MDT.2012.2230297
Filename :
6363530
Link To Document :
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