DocumentCode :
785791
Title :
Throughput-driven floorplanning with wire pipelining
Author :
Casu, Mario R. ; Macchiarulo, Luca
Volume :
24
Issue :
5
fYear :
2005
fDate :
5/1/2005 12:00:00 AM
Firstpage :
663
Lastpage :
675
Abstract :
The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the insertion of flip-flops may alter the throughput of the system due to the presence of loops in the logic netlist. In this paper, we address the problem of floorplanning a large design where long interconnects are pipelined by inserting the throughput in the cost function of a tool based on simulated annealing. The results obtained on a series of benchmarks are then validated using a simple router that breaks long interconnects by suitably placing flip-flops along the wires.
Keywords :
flip-flops; integrated circuit interconnections; integrated circuit layout; network routing; simulated annealing; system-on-chip; wiring; SoC; cost function; flip-flops; long interconnects; simple router; simulated annealing; systems-on-chip; throughput-driven floorplanning; wire pipelining; Clocks; Cost function; Flip-flops; Frequency; Joining processes; Logic; Pins; Pipeline processing; Throughput; Wire; Floorplanning; systems-on-chip (SoC); throughput; wire pipelining;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2005.846371
Filename :
1424170
Link To Document :
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