A novel VLSI architecture of motion compensation for multiple standards

Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264 and the Chinese AVS, many efficient coding tools have been introduced into MC, such as new motion vector prediction, bi-directional matching, quarter precision interpolation, etc. However, these new features enormously increase the computational complexity and the memory bandwidth consumption. In this paper, we introduce a novel architecture design of motion compensation (MC) for multiple video standards including MPEG-2, H.264, and AVS. The proposed design has a macroblock- level pipelined structure which consists of MV predictor, cache-based Fetch, and pixel interpolation unit. The proposed architecture exploits the parallelism in MC algorithm to accelerate the processing speed and uses the dedicated design to optimize the memory access. MV predictor unit can cover all MV prediction algorithms for the three standards and provide a simple error concealment scheme. Cache-based Fetch unit can save 25% memory bandwidth of MC in average and doesn´t impact the performance in the worst case. Pixel interpolation unit adopts fully separate 1D filtering structure which is designed to effectively avoid the redundant calculations. The architecture can achieve the real-time multiple-standard decoding for HDTV 1080i (1920*1088 4:2:0 60 field/s) video. The efficient design can work at the frequency of148.5MHz and the total gate count for logic circuit s is about 56K.